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Wednesday, July 12 • 12:20 - 12:40
5 Level Paging Support in Xen - Yu Zhang, Intel

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Existing Intel processors limit the linear address width to 48 bits, hence the maximum linear address space is 256TiB bytes. Intel's upcoming processor will overcome this limitation by introducing a new paging mode in IA-32e - 5-level paging, which will extend the linear address width to 57 bits and translate linear addresses by traversing a 5-level paging structure.

Also, existing Intel processors limit physical addresses width to 46 bits. That limit applies also to guest-physical addresses. With 5-level paging, the physical address width will be extended to 52 bit. To support VMs with 5 level paging feature, a new EPT mode will be introduced - 5-level EPT. As its name suggests, it will translate guest-physical addresses by traversing a 5-level hierarchy of EPT paging structures.

In this session, Yu will give a introduction of this new feature, and some high level design options to support 5-level paging in Xen.


Yu Zhang

Yu is a virtualization developer from Intel China. Joined Intel open source technology center in 2013, Yu participated in the iGVT-g and iGVT-d projects and currently is devoted to the new feature enabling in Xen/KVM for Intel's next generation CPU. Before joining Intel, Yu had b... Read More →

Wednesday July 12, 2017 12:20 - 12:40
Grand Ballroom

Attendees (10)