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Wednesday, July 12 • 16:35 - 17:35
Design Discussion: Support for 5-level paging (including support for PV-guests) - Yu Zhang, Intel & Jürgen Groß, SUSE

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This session has two parts: if we need more time, we can continue on the next day.

Part 1: Yu Zhang
In this session, Yu will present the audience the current design to support 5 level paging in Xen hypervisor and to support VMs with this new paging mode on Intel's next generation CPU. Hopefully, will get suggestions from community maintainers.

Part 2: Jürgen Groß
Currently Intel is pushing patches to the Linux kernel for support of 5-level paging. This will expand the virtual address space from currently 16TB to 8PB (factor of 512). While supporting 5-level paging in the hypervisor isn't questioned the support for pv-guests has its pros and cons. Especially the pv memory management interface of Xen isn't the best loved interface in the kernel, so expanding it should be done with care, especially considering pvh guests as a replacement for pv.

This session is meant to come to a conclusion what to do about 5-level paging and pv guests.

Speakers
JG

Jürgen Groß

Kernel Virtualization Engineer, SUSE
Jürgen started operating system work in 1989. He has experience in multiple OS's including some UNIX flavors on many different processors (MIPS, SPARC, Itanium, x86) where he did virtualization related work. His first contact with Xen was in 2008 when he enabled the Xen hypervisor on Itanium to run BS2000 (a mainframe OS) as a guest system. Now... Read More →
YZ

Yu Zhang

Intel
Yu is a virtualization developer from Intel China. Joined Intel open source technology center in 2013, Yu participated in the iGVT-g and iGVT-d projects and currently is devoted to the new feature enabling in Xen/KVM for Intel's next generation CPU. Before joining Intel, Yu had b... Read More →



Wednesday July 12, 2017 16:35 - 17:35
Valletta Conference Centre II

Attendees (3)